Since the thickness of stacked silicon chips in 3D integration has been thinned to less than 100 μm, the local thermal deformation of the chips has increased drastically because of the decrease of the flexural rigidity of the thinned chips. The clear periodic thermal deformation and thus, the local distribution of thermal residual stress appears in the stacked chips due to the periodic alignment of metallic bumps, and they sometimes deteriorate mechanical and electrical reliability of electronic products. In this paper, the dominant structural factors of the local residual stress in a silicon chip are investigated quantitatively based on the results of a three-dimensional finite element analysis and the measurement of the local residual stress in a chip using stress sensor chips. The piezoresistive strain gauges were embedded in the sensor chips. The length of each gauge was 2 μm, and an unit cell consisted of four gauges with different crystallographic directions. This alignment of the strain gauges enables us to measure the tensor component of three-dimensional stress fields separately. Test flip chip substrates were made of silicon chip on which the area-arrayed tin/copper bumps were electroplated. The width of a bump was fixed at 200 μm, and the bump pitch was varied from 400 μm to 1000 μm. The thickness of the copper bump was about 40 μm and that of tin layer was about 10 μm. This tin layer was used for the formation of rigid joint by alloying it with copper interconnection formed on a stress sensing chip. The measured amplitude of the residual stress increased from about 30 MPa to 250 MPa depending on the combination of materials such as bump, underfill, and interconnections. It was confirmed that both the material constant of underfill and the alignment structure of fine bumps are the dominant factors of the local deformation and stress of a silicon chip mounted on area-arrayed metallic bumps. It was also confirmed that not only the control of mechanical properties of electroplated copper thin films, but also the hound’s-tooth alignment of a through silicon via and a bump are indispensable for minimizing the packaging-induced stress in the three-dimensionally mounted chips. This test chip is very effective for evaluating the packaging-process-induced stress in 3D stacked chips quantitatively.

References

1.
Koyanagi
,
M.
,
Nakamura
,
T.
,
Yamada
,
Y.
,
Kikuchi
,
H.
,
Fukushima
,
T.
,
Tanaka
,
T.
, and
Kurino
,
H.
, 2006, “
Three-Dimensional Integration Technology Based on Wafer Bonding With Vertical Buried Interconnections
,”
IEEE Trans. Electron Devices
,
53
(
11
), pp.
2799
2808
.
2.
Tanaka
,
N.
,
Kawano
,
K.
,
Miura
,
H.
,
Kada
,
Y.
, and
Yoshida
,
I.
, 2004, “
A Highly Reliable Design for a Nonmetal Lurgical Conract-Joint Structure Consisting of an Adhesive Film
,”
ASME J. Electron. Packag.
,
126
, pp.
82
86
.
3.
Tanida
,
K.
,
Umemoto
,
M.
,
Tomita
,
Y.
,
Tago
,
M.
,
Kawajima
,
R.
,
Akiyama
,
Y.
, and
Takahashi
,
K.
, 2003, “
An Bump Interconnection With Ultrasonic Flip-Chip Bonding in 20 μm Pitch
,”
Jpn. J. Appl. Phys.
,
42
, pp.
2198
2203
.
4.
Ueta
,
N.
, and
Miura
,
H.
, 2005, “
Measurement of Local Residual Stress of a Flip Chip Structure Using a Stress Sensing Chip
,” Proc. of ASME InterPACK’05, Report No. IPACK2005-73112.
5.
Miura
,
H.
,
Ueta
,
N.
, and
Sato
,
Y.
, 2005, “
Local Thermal Deformation and Residual Stress of a Thin Si Chip Mounted on a Substrate Using an Area-Arrayed Flip Chip Structure
,”
Proc. of IEEE EMAP
2005, pp.
220
225
.
6.
Tamakawa
,
K.
,
Sakutani
,
K.
, and
Miura
,
H.
, 2007, “
Effect of Micro Texture of Electroplated Copper Thin Films on Their Mechanical Properties
,”
J. Mater. Sci.
,
56
, pp.
907
912
.
7.
Miura
,
H.
, and
Nishimura
,
A.
, 1994, “
Device Characteristic Changes Caused by Packaging Stress
,”
ASME J. Electronic Packag.
,
AMD-195
, pp.
101
109
.
8.
Miura
,
H.
,
Kumazawa
,
T.
, and
Nishimura
,
A.
, 1995, “
Effect of Delamination at Chip/Encapsulant Interface on Chip Strss and Transistor Characteristics
,”
ASME Application of Experimental Mechanics to Electronic Packaging
,
AMD-196
, pp.
73
78
.
9.
Hamada
,
A.
,
Furusawa
,
T.
,
Saito
,
N.
, and
Takeda
,
E.
, 1991, “
A New Aspect of Mechanical Stress Effects in Scaled MOS Devices
,”
IEEE Trans. Electron Devices
,
38
(
4
), pp.
895
900
.
10.
Murata
,
N.
,
Tamakawa
,
K.
,
Suzuki
,
K.
, and
Miura
,
H.
, 2009, “
Fatigue Strength of Electroplated Copper Thin Films Under Uni-Axial Stress
,”
JSME
,
3
(
3
), pp.
498
506
.
11.
Murata
,
N.
,
Tamakawa
,
K.
,
Suzuki
,
K.
, and
H.
Miura
, 2009, “
Micro Texture Dependence of Mechanical Properties of Electroplated Copper Thin Films Used for Thin Film Interconnection
”, Proc. of ASME InterPACK’09, Report No. IPACK2009-89079.
12.
Murata
,
N.
,
Tamakawa
,
Suzuki
,
K.
, and
H.
Miura
, 2009, “
Thermal History Dependence of Mechanical Properties of Electroplated Copper Thin Films Used for Thin Film Interconnection
,”
Proc. of International Conference on Electronics Packaging 2009
, pp.
911
914
.
13.
Murata
,
N.
,
Saito
,
N.
,
Tamakawa
,
K.
,
Suzuki
,
K.
, and
Miura
,
H.
, 2010, “
Micto Texture Dependence of Both the Mechanical and Electrical Properties of Electroplated Copper Thin Films Used For Interconnection
,”
Proc. of ASME International Mechanical Engineering Congress and Exposition 2010
, Report No. IMECE2010-37279.
14.
Miura
,
H.
,
Kitano
,
M.
,
Nishimura
,
A.
, and
Kawai
,
S.
, 1993, “
Thermal Stress Measurement in Silicon Chips Encapsulated In IC Plastic Packages Under Temperature Cycling
”,
ASME J. Electron. Packag.
,
15
, pp.
9
15
.
15.
Sato
,
Y.
, and
Miura
,
H.
, 2007, “
Development of a Nondestructive Inspection Method for Detecting Open Failures of Micro Bump Interconnections in Three Dimensionally Stacked LSI Chips
,” Proc. of InterPACK 2007, Report No. IPACK2007-33257.
You do not currently have access to this content.