We devise a finite-element model to analyze the thermal performance of collector-up (C-up) heterojunction bipolar transistors (HBTs) with a thermal-via configuration. A demonstration on the GaInP/GaAs C-up HBT is presented in this Brief, and the novelty of this work is that both 2D and 3D temperature-distribution analyses are performed. The 2D results indicate that the original thermal-via configuration can be reduced by 29%. Furthermore, the results show that the maximum temperature within the collector calculated from 3D analysis is lower than that from the 2D analysis. Based on the 3D analysis, it is revealed that the reported configuration can be reduced by 32%. Therefore, the C-up HBT with a compact thermal-via should be helpful for miniaturization of heat-dissipation packaging configurations within HBT-based high-power amplifiers.
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e-mail: j41528@mail.ksu.edu.tw
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December 2009
Technical Briefs
Novel Design of Thermal-Via Configurations for Collector-Up HBTs
Pei-Hsuan Lee,
Pei-Hsuan Lee
Department of Engineering Science,
National Cheng Kung University
, Tainan 70101, Taiwan, R.O.C.
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Hsien-Cheng Tseng,
Hsien-Cheng Tseng
Department of Electronic Engineering and Nanotechnology, R&D Center,
e-mail: j41528@mail.ksu.edu.tw
Kun Shan University
, Tainan 71003, Taiwan, R.O.C.
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Jung-Hua Chou
Jung-Hua Chou
Department of Engineering Science,
National Cheng Kung University
, Tainan 70101, Taiwan, R.O.C.
Search for other works by this author on:
Pei-Hsuan Lee
Department of Engineering Science,
National Cheng Kung University
, Tainan 70101, Taiwan, R.O.C.
Hsien-Cheng Tseng
Department of Electronic Engineering and Nanotechnology, R&D Center,
Kun Shan University
, Tainan 71003, Taiwan, R.O.C.e-mail: j41528@mail.ksu.edu.tw
Jung-Hua Chou
Department of Engineering Science,
National Cheng Kung University
, Tainan 70101, Taiwan, R.O.C.J. Electron. Packag. Dec 2009, 131(4): 044501 (3 pages)
Published Online: October 21, 2009
Article history
Received:
August 21, 2008
Revised:
September 17, 2009
Published:
October 21, 2009
Citation
Lee, P., Tseng, H., and Chou, J. (October 21, 2009). "Novel Design of Thermal-Via Configurations for Collector-Up HBTs." ASME. J. Electron. Packag. December 2009; 131(4): 044501. https://doi.org/10.1115/1.4000282
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