Using detailed finite element models, a fracture analysis of solder bumps and under bump metallurgy (UBM) in flip-chip packages is carried out. Our objective is to identify likely fracture modes and potential delamination sites at or near these microstructural components. In order to study flip-chips, whose dimension spans from sub-micron thickness UBM layers to several millimeters wide package, we have applied a multi-scale finite element analysis (MS-FEA) procedure. In this procedure, initially, deformation of whole thermally loaded package is analyzed. Then, the results are prescribed as the boundary conditions in a very detailed cell model, containing a single solder bump, to investigate micro-deformation surrounding UBM. Using the models with two different scales, accurate stress fields as well as fracture parameters of various interface cracks can be determined. The MS-FEA is ideally suited for the flip-chip packages since they contain many identical solder bumps. A cell model can be repeatedly used to probe stress and fracture behaviors at different locations. The computed results show high stress concentrations near the corners of solder bumps and UBM layers. Based on the energy release rate calculations, solder bumps located near the edge of chip are more likely to fail. However, our results also suggest possible delamination growth at solder bumps near the center of chip. In addition, we have observed increasing energy release rates for longer cracks, which implies a possibility of unstable crack growth.
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September 2001
Papers On Reliability
Interfacial Delamination Near Solder Bumps and UBM in Flip-Chip Packages
Yu Gu,
Yu Gu
Department of Mechanical Engineering, State University of New York at Stony Brook, Stony Brook, NY 11794
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Toshio Nakamura, Mem. ASME,
Toshio Nakamura, Mem. ASME
Department of Mechanical Engineering, State University of New York at Stony Brook, Stony Brook, NY 11794
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William T. Chen,
William T. Chen
Institute of Materials Research and Engineering, 3 Research Link, Singapore 117602
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Brian Cotterell
Brian Cotterell
Institute of Materials Research and Engineering, 3 Research Link, Singapore 117602
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Yu Gu
Department of Mechanical Engineering, State University of New York at Stony Brook, Stony Brook, NY 11794
Toshio Nakamura, Mem. ASME
Department of Mechanical Engineering, State University of New York at Stony Brook, Stony Brook, NY 11794
William T. Chen
Institute of Materials Research and Engineering, 3 Research Link, Singapore 117602
Brian Cotterell
Institute of Materials Research and Engineering, 3 Research Link, Singapore 117602
Contributed by the Electrical and Electronic Packaging Division for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received by the EEPD December 1999; revised manuscript received August 2000. Associate Editor: G. De Mey.
J. Electron. Packag. Sep 2001, 123(3): 295-301 (7 pages)
Published Online: August 1, 2000
Article history
Received:
December 1, 1999
Revised:
August 1, 2000
Citation
Gu , Y., Nakamura, T., Chen , W. T., and Cotterell , B. (August 1, 2000). "Interfacial Delamination Near Solder Bumps and UBM in Flip-Chip Packages ." ASME. J. Electron. Packag. September 2001; 123(3): 295–301. https://doi.org/10.1115/1.1348338
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