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Research Papers

Competing Fracture of Thin-Chip Transferring From/Onto Prestrained Compliant Substrate

[+] Author and Article Information
Huimin Liu

State Key Laboratory of Digital Manufacturing
Equipment and Technology,
Flexible Electronics Research Center,
Huazhong University of Science and Technology,
Wuhan 430074, China;
Department of Weaponry Engineering,
Naval University of Engineering,
Wuhan 430033, China
e-mail: 25731014@qq.com

Zunxu Liu

State Key Laboratory of Digital Manufacturing
Equipment and Technology,
Flexible Electronics Research Center,
Huazhong University of Science and Technology,
Wuhan 430074, China
e-mail: zunxuliu@hust.edu.cn

Zhoulong Xu

State Key Laboratory of Digital Manufacturing
Equipment and Technology,
Flexible Electronics Research Center,
Huazhong University of Science and Technology,
Wuhan 430074, China
e-mail: birdnest@qq.com

Zhouping Yin

State Key Laboratory of Digital Manufacturing
Equipment and Technology,
Flexible Electronics Research Center,
Huazhong University of Science and Technology,
Wuhan 430074, China
e-mail: yinzhp@hust.edu.cn

YongAn Huang

State Key Laboratory of Digital Manufacturing
Equipment and Technology,
Flexible Electronics Research Center,
Huazhong University of Science and Technology,
Wuhan 430074, China
e-mail: yahuang@hust.edu.cn

Jiankui Chen

State Key Laboratory of Digital Manufacturing
Equipment and Technology,
Flexible Electronics Research Center,
Huazhong University of Science and Technology,
Wuhan 430074, China
e-mail: chenjk@hust.edu.cn

1Huimin Liu and Zunxu Liu contributed equally to this work.

2Corresponding authors.

Contributed by the Applied Mechanics Division of ASME for publication in the JOURNAL OF APPLIED MECHANICS. Manuscript received May 27, 2015; final manuscript received July 12, 2015; published online July 30, 2015. Editor: Yonggang Huang.

J. Appl. Mech 82(10), 101012 (Jul 30, 2015) (10 pages) Paper No: JAM-15-1271; doi: 10.1115/1.4031047 History: Received May 27, 2015

The transferring of thin chip from donor to receptor plays a critical role in advanced electronic package, and the productivity is determined by the interfacial behavior between chip and substrate during chip transferring. The paper investigates analytical competing fracture model of chip–adhesive–substrate structure in thin-chip transferring (peeling-off and placing-on), to discover the critical process condition for distinguishing the interfacial delamination and chip crack. The structure is continuously subjected to ejecting needle, vacuum pick-up head, and wafer fixture, which leads to concentrated and distributed loads and dynamic boundary conditions. Additionally, two criterions based on competing fracture model are presented to determine the extreme chip dimension for peeling-off and the elimination of residual stress for placing-on. The theoretical results are validated by the finite-element simulation with virtual crack-closure technique (VCCT). This paper provides an insight for process optimization, to improve the success ratio and productivity of chip transferring.

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References

Figures

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Fig. 1

(a) Schematics of chip-transferring process, (b) peeling process of chip from adhesive substrate, (c) chip–adhesive–substrate structure, and (d) four stages of chip transferring in flip-chip process

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Fig. 2

Mechanics model of multilayer structure: (a) chip–adhesive–substrate with bending moments, axial and transverse loads acting on a segment of delaminated chip–adhesive–substrate structure immediately behind and ahead of the crack tip and (b) the half of the chip–adhesive–substrate structure

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Fig. 3

Three phases in peeling of chip from substrate

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Fig. 4

The ERR and mode angle as functions of the chip size: (a) the length and (b) the thickness

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Fig. 5

Chip cracking of a radio frequency indentification (RFID) chip, with pierce-through crack on the center: (a) chip cracking of a RFID chip, with pierce-through crack on the center and (b) two competing failure modes

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Fig. 6

The interfacial ERR and chip cracking stress as functions of chip thickness and length

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Fig. 7

(a) Mode II ERR as a function of the distance between the chips. The chip length is fixed at lchip = 1.0 mm, and the distance between chips, 2lvacancy, varies from 0.04 mm to 4.0 mm. (b) Mode II ERR as a function of the chip size.

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Fig. 8

Maximum ERR as a function of the chip size and Young's modulus of substrate. Two critical fracture toughness of the adhesive layer, Γadhesive = Γa = 0.0035 N/mm and Γadhesive = Γa = 0.002 N/mm, are added in the figure as the dash line.

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Fig. 9

Interfacial shear stress related with thickness and web tension stress, where the deposit temperature is (a) Tdeposition = 150 °C and (b) Tdeposition = 200 °C

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Fig. 10

(a) Comparison of two design methods (interface-based method and moment-based method) and (b) design based on material, structure, and processes

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